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This paper describes the architecture of PACE3 and the key design parameters for a large dynamic range front-end amplification and low noise analog memory. Measured results from PACE3 are presented characterizing the chip's performance in terms of gain, pulse shaping characteristics, noise, power consumption and radiation tolerance with respect to total ionizing dose and robustness to single event upsets (SEU).
Nuclear Science Symposium Conference Record, 2005 IEEE (Volume:2 )
Date of Conference: 23-29 Oct. 2005