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Design of on-chip and off-chip interfaces for a GALS NoC architecture

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2 Author(s)
Beigne, E. ; CEA-LETI, Grenoble ; Vivet, P.

In this paper, we propose the design of on-chip and off-chip interfaces adapted to a globally asynchronous locally synchronous (GALS) network-on-chip (NoC) architecture. The proposed on-chip interface not only handles the resynchronization between the synchronous and asynchronous NoC domains, but also implements NoC communication priorities. This design is based on existing multi-clock synchronization fifos based on Gray code, and is adapted to standard implementation tools. Concerning Off-chip communications, a new concept of mixed synchronous/asynchronous dual mode NoC port is proposed as an efficient off-chip NoC interface for NoC-based open-platform prototyping. These interfaces have been successfully implemented in a 0.13mum CMOS technology

Published in:

Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium on

Date of Conference:

13-15 March 2006

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