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Fast asynchronous shift register for bit-serial communication

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3 Author(s)
Dobkin, R. ; VLSI Syst. Res. Center, Technion-Israel Inst. of Technol., Haifa ; Ginosar, R. ; Kolodny, A.

A fast asynchronous shift register is used as the serializer and deserializer in a novel bit-serial on-chip communication link. The link employs two-phase transition-based LEDR encoding. Acknowledgement is generated only at the word level, rather than bit by bit. The shift register is designed to achieve bit time of a single gate delay. It is based on a wave-pipelined control path and on transition latches. The circuit achieved 67 Gbps data rate when simulated on 65nm CMOS technology and was immune to in-die process variations of up to 10sigma

Published in:

Asynchronous Circuits and Systems, 2006. 12th IEEE International Symposium on

Date of Conference:

13-15 March 2006