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System-level modeling and validation increase design productivity and save errors

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1 Author(s)
Chown, B. ; Mentor Graphics, Wilsonville

As the complexity of system on chip (SoC) devices rises to include scores, in some cases hundreds, of distinct blocks, system validation becomes a critical concern. A variety of techniques have emerged to help designers verify that individual blocks of a device meet performance specification. But what about functional intent? Are performance goals achieved? In this paper, we make the case for high-level system validation before RTL implementation, and present a flow to approach this increasingly essential task.

Published in:

System-on-Chip, 2005. Proceedings. 2005 International Symposium on

Date of Conference:

17-17 Nov. 2005