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Delay modeling and static timing analysis for MTCMOS circuits

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2 Author(s)
Ohkubo, N. ; Graduate Sch. of Eng., Shibaura Inst. of Technol., Saitama ; Usami, K.

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy

Published in:

Design Automation, 2006. Asia and South Pacific Conference on

Date of Conference:

24-27 Jan. 2006