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High-throughput decoder for low-density parity-check code

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4 Author(s)
Ishikawa, T. ; Graduate Sch. of Inf., Production & Syst., Waseda Univ., Fukuoka ; Shimizu, K. ; Ikenaga, T. ; Goto, S.

We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304 bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18mum, 6 metal-layer CMOS technology. The chip size is 36mm2

Published in:

Design Automation, 2006. Asia and South Pacific Conference on

Date of Conference:

24-27 Jan. 2006