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This paper addresses the problem of minimizing both leakage and glitch power by appropriately using dual-Vth and buffer insertion (for path balancing) techniques, respectively. The problem is formulated as an integer linear program (ILP) with the objective of optimally assigning threshold voltage to the gates to minimize total leakage power and then inserting delay buffers at appropriate positions to minimize glitches. The ILP allows for tradeoff analysis by including constraints where user specified thresholds for total leakage power as well as circuit performance can be inserted. The ILP is solved using CPLEX. Simulation results with ISCAS'85 benchmark circuits indicate that significant savings in leakage power is achieved with minimal number of inserted buffers.