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This paper presents a novel, power-efficient architecture for decimation filter which is a critical component in multistandard digital receivers. Cascade integrator comb (CIC) filter is used to reduce high data rate because of its straightforward structure composed of adders and delays. The proposed power reduction is obtained by designing the integrator section as a polyphase structure where each polyphase component operates at reduced frequency. The digital receiver must process the in-phase (I) and quadrature (Q) signals using two similar filters. This structure is modified to process both signals with interleaved techniques. Thus, just one structure is needed to perform this operation over the two signals. Additionally, reduced frequency operation on the new structure allows us to use low power circuit design techniques such as voltage scaling to reduce the power consumption without affecting the performance of the whole structure. Power-intensive multiplications required for the polyphase filter components are replaced by add-and-shift multiplications. Different communication standards such as data networks (Mobitex and Ardis) and cellular networks (GSM, IS-95, and UMTS) are considered in the filter design. The architecture has been designed, and analyzed. Power estimation shows that the new architecture consumes only 15% of the power of the original structure (i.e., a savings of 85%).