Implementation of novel low-power driver for integrated buck converter

In this paper, we design the best fit driver for power transistors of the synchronous buck PWM converter for turning on and off and generating the desired output. To find the best fit driver, four circuits were implemented using 0.18 mum CMOS technology, and cadence was used to simulate and verify the functionality of these circuits. The design criteria of these drivers depend on power dissipation, delay, and physical size. The best design consists of the novel buck driver with the synchronous DC-DC buck converter. The DC input voltage of this design was 1.2 V, and the DC output voltage of this design was 1.0 V along with output current was 120 mA. The maximum frequency range of this design was up to 100 MHz. The total size of this converter was around 154 mm² plus the area of the inductor and capacitor. The designed converter achieved the required specification, and its efficiency was up to 94.9%