A novel low area and high performance programmable FIR filter design using dynamic random access memory

We present a novel low area, and high performance data memory design for storing intermediate partial products in a programmable FIR filter. The advantage in area comes because the memory is implemented as DRAM in place of frequently used SRAM. A technique of storing data with reduced bit precision has been demonstrated to reduce area without compromising on round-off noise. Power advantage comes because no rewrite is required in this architecture after destructive read from DRAM. At high operating frequencies, simulation results in 0.2 /spl mu/m technology for a 48 tap FIR filter with DRAM shows an improvement in transistor count by 50% and power by 30% over SRAM.