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Design of a 3.3-V 1.2-GHz pipelined multiplier to implement energy-efficient multimedia applications

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3 Author(s)
M. Aguirre ; Dept. of Electron., INAOE-Mexico, Puebla, Mexico ; M. Salim ; M. Linares

This paper presents the design of a high-speed low-power 8×8-bits pipelined multiplier, built upon a full adder cell implemented with an alternative internal logic structure that uses the C input signal to select XOR/XNOR and AND/OR logic functions, to get the sum and carry outputs, respectively. Furthermore, the full adder cell was designed using a swing-restored complementary pass-transistor logic style in order to avoid static power dissipation and to have a complete voltage swing at internal nodes to enable a faster operation. The multiplier has been designed with a 0.35μm CMOS technology, and it is able to operate up to 1.2GHz when supplied with 3.3V. Post-layout simulations have been carried out for this multiplier and other ones previously published, in order to compare their performance on regards of speed and power dissipation. The results show that the power savings obtained for the proposed multiplier are about 20% when operating with transitioning input data, over 95% with stable input data and 90% with the clock signal disabled.

Published in:

48th Midwest Symposium on Circuits and Systems, 2005.

Date of Conference:

7-10 Aug. 2005