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Dynamic reconfigurable distributed processing network with dual levels of operand granularity

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3 Author(s)
Vallina, F.M. ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL ; Oruklu, E. ; Saniie, J.

This paper introduces a platform capable of handling varying operand sizes across a set of algorithms to be accelerated by a low power hardware core. The key to dealing with different levels of operand granularity is to implement them on the reconfigurable distributed processing network (RDPN), which can handle dynamic changes to operand size. This approach allows algorithms which may be incompatible for the same hardware platform to be accelerated by a common hardware core. This acceleration core based on the RDPN allows algorithms of different levels in operand granularity to be accelerated by a low power system without the need for extra logic. The RDPN architecture provides a flexible platform, which bridges the gap between software and hardware by extending the applicability of an embedded hardware system. This extended applicability is a result of the native support for word size extension and contraction within the RDPN computational fabric. A case study from the signal processing algorithmic domain will be presented to show how the RDPN fabric dynamically adapts to the operand granularity required by different stages of an algorithm

Published in:

Circuits and Systems, 2005. 48th Midwest Symposium on

Date of Conference:

7-10 Aug. 2005