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A CMOS broadband divide-by-32/33 dual modulus prescaler for high speed wireless applications

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2 Author(s)
Golsa Ghiaasi ; Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH ; Ismail, M.

This paper describes the design of a divide-by 32/33 dual modulus prescaler for high speed broadband applications in CMOS 0.18 mum technology. The design uses extended true single phase clock (E-TSPC) logic to decrease the power consumption and enhance the noise performance. The prescaler operates over a wide range of frequencies: 210 MHz to 5.3 GHz. It makes the circuit suitable for multiband multimode operation. The circuit drains only 2.53 mW from a 1.8 V supply voltage. The achieved noise floor is -167 dBc/Hz at 3 GHz

Published in:

Circuits and Systems, 2005. 48th Midwest Symposium on

Date of Conference:

7-10 Aug. 2005