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Symbolic verification of synthesized RTL using Boolean satisfiability and uninterpreted RTL transformations

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4 Author(s)
Sundaresan, V. ; Dept. of ECECS, Cincinnati Univ., OH ; Radhakrishnan, R. ; Siva, S. ; Vemuri, R.

We present a symbolic verification methodology to verify the register transfer logic (RTL) design generated during high-level synthesis (HLS) against the behavioral specification. The significant contributions of this paper are the following: (i) a symbolic verification methodology capable of verifying synthesis decisions at various stages of HLS; (ii) the use of SAT tool as the main verification engine - this enables the verification methodology to handle larger designs when compared with BDD-based methodologies; (iii) a exploitation of a set of uninterpreted RTL transformations that aid equivalence checking using SAT tools, and provide better diagnostics

Published in:

Circuits and Systems, 2005. 48th Midwest Symposium on

Date of Conference:

7-10 Aug. 2005