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Jitter requirements of the sampling clock in software radio receivers

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3 Author(s)
V. J. Arkesteijn ; IC-Design Group, Univ. of Twente, Netherlands ; E. A. M. Klumperink ; B. Nauta

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:53 ,  Issue: 2 )