High quality uniform random number generation for massively parallel simulations in FPGA

This paper details the design and implementation of three uniform random number generators for use in massively parallel simulations in FPGAs. The three different generators are tailored to make use of three different types of hardware resource: logic, RAM, and DSP blocks. This allows the random number generator to be fitted into resources left-over after the main application has been written. The three generators all pass the most stringent empirical statistical tests for randomness, and all have periods appropriate for long running simulations