Cart (Loading....) | Create Account
Close category search window

A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Pandya, V. ; Sch. of Eng., Guelph Univ., Ont., Canada ; Areibi, S. ; Moussa, M.

General purpose processors (GPPs) and ASICs have traditionally been the common means for building and implementing artificial neural networks (ANNs). However such computing paradigms suffer from the constant need of establishing a trade-off between flexibility and performance. Due to the technological advance in the development of programmable logic devices, field programmable gate arrays (FPGAs) have become attractive for realizing ANNs. FPGAs have shown to exhibit excellent flexibility in terms of reprogramming the same hardware and at the same time achieving good performance by enabling parallel computation. In this paper various implementations of ANNs on FPGAs are investigated and compared. The research described in this paper proposes three partially parallel architectures and a fully parallel architecture to realize the back-propagation algorithm on an FPGA. The proposed designs are coded in Handel-C and functionally verified by synthesizing them on a Virtex2000e FPGA chip. The partially parallel architectures and the fully parallel architecture are found to be 2.25 and 4 times faster than the software implementation respectively for different benchmarks.

Published in:

Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International Conference on

Date of Conference:

28-30 Sept. 2005

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.