Queue usage and memory-level parallelism sensitive scheduling

In out-of-order (OOO) processors, reorder queue (ROQ) has been widely used to implement precise interruption. The full of ROQ will cause the whole processor stall, while a long latency operation, e.g. a load missed in the caches, will almost definitely cause the ROQ full. In this paper, we present a model for estimating the impact of issuing an instruction on the usage of ROQ and memory level parallelism (MLP), and incorporate these considerations in the cost model of instruction scheduling. Preliminary evaluation results are presented to demonstrate the effectiveness of our approach on reducing the time of ROQ full and improving performance.