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Performance evaluation of circuit switched multistage interconnection networks using a hold strategy

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2 Author(s)
S. -H. Hsiao ; Syracuse Univ., NY, USA ; C. Y. R. Chen

The performance evaluation of processor-memory communications for multiprocessor systems using circuit switched interconnection networks with a hold strategy is performed. Message size and processor processing time are considered and shown to have a significant effect on the overall system performance. A closed queuing network model is proposed such that only (n+2) states are required by the proposed model, in contrast to (n2+3n+4)/2 states needed in previous studies, where n is the number of stages of the multistage interconnection network. Since a closed-form solution is obtained, the behavior of a complete cycle of memory access through multistage interconnection networks can be accurately analyzed and various performance bounds can be obtained

Published in:

IEEE Transactions on Parallel and Distributed Systems  (Volume:3 ,  Issue: 5 )