Skip to Main Content
In contrast to software implementation, hardware implementation of encryption protocols provides a higher level of security and cryptography speed at some flexibility cost. In this paper, different existing implementations of Advanced Encryption Standard (AES) are considered and a fully pipelined implementation for the AES is presented. Implementation considers both encryption and decryption. The design is optimized for achieving higher speed and lower area cost. The Selected algorithm for our design is Rijndael. The major part of an AES design is designing substitute boxes (S-box). S-boxes in our design are implemented at a lower cost rather than the existing implementations. Throughput of up to 6 Gbps is gained by our proposed architecture. This implementation is equipped with BIST architecture for self testing.