Design and Implementation of Viterbi Encoding and Decoding Algorithm on FPGA

In this paper we have presented the hardware design implementation of Viterbi encoding and decoding algorithm. We have developed our own approach for the design of a 2/3 bit rate encoder and decoder. Convolution coders which are designed with shift registers and modulo-2 adders have been outlined. Viterbi decoder section includes Branch Metric Unit (BMU), Add Compare Select Unit (ACSU), Normalization Unit, Decision Unit and Output Unit have been implemented for 2/3 bit rate. The design has been implemented on Virtex II FPGA using XILINX 6.1i software with supporting simulation tool Modelsim 5.7. The results obtained from synthesis, simulation and hardware testing were accurate, error-free and original information was recovered successfully.