A Simple, Low-Cost and Low-Power Switch Architecture for NoCs

Considering the typically large use of NoCs as a solution to alleviate complexity of the current SoCs, designing an efficient NoC is an important key issue. This paper proposes a simple, low-cost and low-energy switch architecture for the NoCs using mesochronous clocking scheme for on-chip communication. Switches are designed in Verilog HDL. Experimental results show that the 4-ports instances of our proposed architecture are more efficient to be used as a basic element for constructing the NoCs.