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In this paper, a new high performance yet low power circuit technique called merged differential cascode voltage switch with pass-gate (MDCVSPG) is introduced. It combines the benefits of two logic styles of EDCVSL and DCVSPG. To verify the efficiency of the proposed logic, gates NAND, NOR, and XOR for the logic styles are simulated using HSPICE. The results show better performance and lower power consumption for MDCVSPG compared to EDCVSL and DCVSPG. In addition, when is used in design of an 8 bit ripple carry adder, the proposed style consumes 38% less silicon area compared to DCVSPG. The area efficiency is due to a reduction of transistor number and layout complexity.
Date of Conference: 13-15 Dec. 2005