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Hardness-by-design approach for 0.15 μm fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

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11 Author(s)
Makihara, A. ; High-Reliability Components Corp., Ibaraki, Japan ; Midorikawa, M. ; Yamaguchi, T. ; Iide, Y.
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We designed logic cells hardened for single-event upsets/single-event transients (SEUs/SETs) using hardness-by-design (HBD) methodology on OKI's 0.15 μm fully depleted complementary metal-oxide-semiconductor/silicon-on-insulator (CMOS/SOI) commercial process and evaluated the sample devices. Our previous work demonstrates that SET-free inverters can be successfully applied as SEU-immune latches. In this paper, the native latches are redesigned using SET-free inverters not only for the inverter loop but also for several types of clock gates (L-SETfree-LoopCK, L-SETfree-LoopCK-SmallArea, and L-SETfree-LoopCK-AddTr.). In addition, the native combinational logic cells are redesigned using SET-free inverters as SET-free NAND and SET-free NOR . Excellent SEU/SET hardness of the HBD latches were achieved up to LET of 64 MeV/(mg/cm2).

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Nuclear Science, IEEE Transactions on  (Volume:52 ,  Issue: 6 )