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HBD using cascode-Voltage switch logic gates for SET tolerant digital designs

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4 Author(s)
Casey, M.C. ; Electr. Eng. & Comput. Sci. Dept., Vanderbilt Univ., Nashville, TN, USA ; Bhuva, B.L. ; Black, J.D. ; Massengill, L.W.

Cascode-voltage-switch logic family of gates is evaluated for single-event vulnerability. As the data is stored on two storage nodes for each logic gate in this logic family, as opposed to only one for static logic family, the single-event transient pulse does not propagate for more than a few stages. Simulation results show single-event transient pulse termination after one logic gate. Area, speed, and power requirements for cascode-voltage logic are comparable to that of static logic.

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Nuclear Science, IEEE Transactions on  (Volume:52 ,  Issue: 6 )