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Expensive and time-consuming three-dimensional (3-D) simulations have been previously employed to characterize single-event upsets of integrated circuits. This paper outlines a more practical engineering approach to SOI single-event effects modeling that involves simple closed-form one-dimensional (1-D) solutions to the carrier transport equations. Using Fourier analysis, the transport equations have direct 1-D closed form solutions for "low injection" conditions. One-dimensional numerical solutions are also obtained for "high injection" conditions (i.e., when the excess injected carrier concentration exceeds the background doping), including other nonlinearities such as the dependence of mobility on both the background concentrations and excess carrier concentrations. The 1-D equations for low injection are reasonable approximations for high injection in n-type material, but not for high injection in p-type material. However, a simple 1-D equation can still be used for high injection in p-type material. The 1-D equations are used with existing simple SPICE models, including models for the parasitic bipolar transistors. The 1-D model agrees well with predictions from 2-D and 3-D simulations. A circuit cell layout can be broken into various regions with differing SEU sensitivities, each with its own characterizing 1-D equation. This simple method leads to a theoretical prediction of cross-sectional area versus upset linear energy transfer (LET) that is in good agreement with experimental heavy ion SEU data for an SRAM. The method also accounts for strike angles in three dimensions.