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A new technique is described for reducing computational complexity and improving accuracy of combined power distribution and interconnect noise prediction for wide, on-chip data-buses. The methodology uses lossy transmission-line power-blocks with frequency-dependent properties needed for the multigigahertz clock frequencies. The interaction between delta-I noise, common-mode noise, and crosstalk and their effect on timing is illustrated with simulations using representative driver and receiver circuits and on-chip interconnections.
Date of Publication: Feb. 2006