Skip to Main Content
This letter presents the design and implementation of a dual-modulus (64/65) prescaler based upon the phase-switching technique. Low power consumption is achieved by using one dynamic flip-flop in the full-speed divide-by-four circuit and no power-hungry synchronizing circuits to tackle the glitch problem. The proposed design is fabricated using 0.35-μm standard CMOS process and is measured to operate from 2.08-2.66GHz with power dissipation of less than 1mW.
Date of Publication: Feb. 2006