By Topic

A stacked-CMOS cell technology for high-density SRAM's

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Y. Uemoto ; Matsushita Electron. Corp., Osaka, Japan ; E. Fujii ; A. Nakamura ; K. Senda
more authors

A stacked-CMOS SRAM cell technology for high-density SRAMs has been developed. It has been found that the increase of the on-current of the thin-film transistor (TFT) load leads not only to the increase of the cell noise margin, but also to the reduction of the cell area. The improvement of the electrical characteristics of the TFT load has been achieved by enlarging the grains of the polysilicon film through the use of a novel solid-phase growth technique. As a result, TFT loads with on/off current ratio of 105 and off-current of 0.07 pA/μm, both promising for high-density SRAMs, have been obtained

Published in:

IEEE Transactions on Electron Devices  (Volume:39 ,  Issue: 10 )