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Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers

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5 Author(s)
Jian Chen ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Solomon, R. ; Chan, T.-Y. ; Ko, P.K.
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C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed

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Electron Devices, IEEE Transactions on  (Volume:39 ,  Issue: 10 )