By Topic

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hori, T. ; Matsushita Electric Ind. Co. Ltd., Osaka, Japan ; Hirase, J. ; Odake, Y. ; Yasui, T.

Deep-submicrometer large-angle-tilt implanted drain (LATID) technology is described. It is found by Monte Carlo process simulation and SIMS measurements that a sufficiently long n- region can be formed under the gate by taking advantage of large-angle-tilt implant and successfully without ion channeling by taking care of the implant direction. A design that offsets the n+ implant by sidewall spacers to suppress the n+-gate overlap to zero while keeping the n- region fully overlapped with the gate is found to be crucial for improved performance and reliability. The device performance, such as current drivability and short-channel effects, is described, and the circuit speed is investigated. Hot-carrier effects such as lateral electric field and device lifetime over a wide range of drain structures are also investigated. The tradeoff between device performance and hot-carrier reliability in deep-submicrometer LATID FETs is discussed

Published in:

Electron Devices, IEEE Transactions on  (Volume:39 ,  Issue: 10 )