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An L-band CMOS frequency doubler using a time-delay technique

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2 Author(s)
Jackson, B.R. ; Dept. of Electr. & Comput. Eng., Queen''s Univ., Kingston, Ont. ; Saavedra, C.E.

In this paper, a frequency doubler circuit is presented that converts a 0.6 GHz signal to a 1.2 GHz output using standard CMOS 0.18 mum technology. The proposed circuit uses a time-delay element and an XOR logic gate to perform the frequency multiplication and is implemented entirely on-chip. Advantages of this topology include good fundamental suppression, compact layout, and low power consumption. Experimental results show a relatively constant output power of approximately 4 dBm with an input power from -3 dBm to 10 dBm, fundamental and third order harmonic suppressions of up to -30 dBc and a power consumption of 9 mW. The phase noise of the output signal is -117 dBc at a 500 kHz offset

Published in:

Silicon Monolithic Integrated Circuits in RF Systems, 2006. Digest of Papers. 2006 Topical Meeting on

Date of Conference:

18-20 Jan. 2006

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