By Topic

A New Approach to Derive Robust Tests for Stuck-Open Faults in CMOS Combinational Logic Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Jhing-Fa Wang ; Institute of Electrical and Computer Engineering, National Cheng Kung University, Tainan, Taiwan, R.O.C. ; Tah-Yuan Kuo ; Jau-Yien Lee

In this paper, we address the problem of deriving robust tests for single stuck-open faults in CMOS combinational circuits. We first examine the characteristics of the transition of the two patterns belonging to a two-pattern test. Then, a sufficient and necessary condition for a test to be robust is given. According to the given condition, we propose a new method to derive robust tests. Robustness verification of the derived tests is no longer required when using our approach.

Published in:

Design Automation, 1989. 26th Conference on

Date of Conference:

25-29 June 1989