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Simplification of a multi-level network is used to perform form transformations on parts of the network to obtain an alternate structure that is optimal with respect to area. A technique for obtaining such an optimal structure involves the use of two-level logic minimization on the components of the multi-level logic network. At each component, the structure of the network is captured by intermediate and fan-out don't care sets, which are utilized in the two-level minimization. However, the generation of all the don't cares yield very large sets for most networks and consequently the complete minimization of the components of the circuits require a very large amount of computer time. In this paper we describe algorithms to reduce the size of the don't care sets, so that only the portions that will be useful in minimization at each component of the circuit are retained. We develop both an exact filter and a heuristic filter that prove to be very effective for a large set of benchmark examples. Results show that our technique achieves the same quality as that obtained by doing complete minimizations at each component of the circuits but in much shorter time. This new approach to simplification of multi-level networks has been incorporated into the MIS (version 2.1) logic synthesis system.