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In this paper I present the algorithms, architecture, and performance of the FAST-1, a special-purpose data-driven computer for switch-level simulation of VLSI circuits. The FAST-1 algorithm computes the same steady state as Bryant's Mossimil algorithm, using a similar network model. The architecture of the simulation machine follows directly from the simulation algorithm and, like the algorithm, is very simple. While the machine has not yet been implemented in hardware, a software-implementation of the proposed architecture has allowed the architecture's performance to be measured in terms of the number of Read-Modify-Write memory cycles required to perform a given simulation. Measurements of circuits ranging in size from a hundred to over 20K transistors indicate that a hardware implementation of the simulation machine will run orders of magnitude faster than software-implemented simulators running on general-purpose computers built using similar technology.