By Topic

Yield Analysis Modeling

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Perry, S. ; NCA Corporation, Santa Clara, CA ; Pilling, D. ; Mitchell, M.

The traditional use of a design rule checker (DRC) ensures that the layout of an integrated circuit conforms to a set of tolerences known as design rules. Integrated circuit manufacturing yields are enhanced if these tolerences are not violated. In contrast to tolerence checking, yield analysis concerns itself with "yield sensitive elements" such as number of devices, total areas and total length of lines. The cumulative distributions of the elements can be used in yield analysis modeling. In addition, the value distribution of each element can be used to model the processing effort required for yielding a design. A software system known as YIELD is essential for extracting the required statistical data from the graphical data base.

Published in:

Design Automation, 1985. 22nd Conference on

Date of Conference:

23-26 June 1985