Skip to Main Content
The traditional use of a design rule checker (DRC) ensures that the layout of an integrated circuit conforms to a set of tolerences known as design rules. Integrated circuit manufacturing yields are enhanced if these tolerences are not violated. In contrast to tolerence checking, yield analysis concerns itself with "yield sensitive elements" such as number of devices, total areas and total length of lines. The cumulative distributions of the elements can be used in yield analysis modeling. In addition, the value distribution of each element can be used to model the processing effort required for yielding a design. A software system known as YIELD is essential for extracting the required statistical data from the graphical data base.