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Magic's Incremental Design-Rule Checker

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2 Author(s)
Taylor, G.S. ; Computer Science Division, Electrical Engineering and Computer Sciences Department, University of California, Berkeley, CA ; Ousterhout, J.K.

The Magic VLSI layout editor contains an incremental design-rule checker. When the circuit is changed, only the modified areas are rechecked. The checker runs continuously in background to keep information about design-rule violations up-to-date. This paper describes the basic rule checker, which operates on edges in the layout, and the techniques used to perform incremental checking on hierarchical designs.

Published in:

Design Automation, 1984. 21st Conference on

Date of Conference:

25-27 June 1984