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Following a UK Department of Industry initiative, the UK5000 project was launched in July 1981 on a 2 year timescale by 7 autonomous UK organizations with different computer systems. The activity involved the collaborative development of an integrated design system for a 5000 gate CMOS array. The DA system was to be portable and capable of generating layouts and test programs from logic circuit descriptions in a time of the order of one week. The CMOS array is unique in containing rows of dedicated bistables, preformed on chip into a shift loop for scan path testing with a totally synchronous clocking scheme. The dedicated bistables, clock lines, shift loops etc, together with the synchronous design lead to lower routeing requirements, elimination of timing hazards and excellent testability.