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An Analytical Method for Compacting Routing Area in Integrated Circuits

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2 Author(s)
Ciesielski, M.J. ; University of Rochester, Rochester, NY ; Kinnen, E.

An analytical method is proposed for solving a routing area compaction problem in building block integrated circuits. Related minimization is performed with a linear programming technique. Minimum channel dimensions are calculated for a preliminary routing; these dimensions are used to construct routing constraints. Placement constraints are added for the interrelations between placement and routing. This combined set of constraints leads to a least overestimation of routing area and under certain conditions guarantees routing feasibility. Computational complexity and existence of a solution are discussed.

Published in:

Design Automation, 1982. 19th Conference on

Date of Conference:

14-16 June 1982

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