Referenced Items are not available for this document.
We propose a clock-domain-based partitioning technique for practicing scan test in large system-on-chips with multiple clock domains with the intent of reducing test application time and test power
Published in:
Test Conference, 2005. Proceedings. ITC 2005. IEEE International
Date of Conference: 8-8 Nov. 2005
- Page(s):
- 9 pp. - 377
- Print ISBN:
- 0-7803-9038-5
- INSPEC Accession Number:
- 9004549
- Conference Location :
- Austin, TX
- Digital Object Identifier :
- 10.1109/TEST.2005.1583995
- Product Type:
- Conference Publications
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