By Topic

A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Arasu, S.T. ; ASIC Dept., Texas Instrum. India, Bangalore ; Ravikumar, C.P. ; Nandy, S.K.

We propose a clock-domain-based partitioning technique for practicing scan test in large system-on-chips with multiple clock domains with the intent of reducing test application time and test power

Published in:

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Date of Conference:

8-8 Nov. 2005