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Test methodology for Freescale's high performance e600 core based on PowerPC/spl reg/ instruction set architecture

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6 Author(s)
Tendolkar, N. ; Somerset Design Center, Freescale Semicond. ; Belete, D. ; Razdan, A. ; Reyes, H.
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This paper presents the DFT techniques used in Freescale's high performance e600 core. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 98% stuck-at-fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when it is integrated in an SoC or host processor

Published in:

Test Conference, 2005. Proceedings. ITC 2005. IEEE International

Date of Conference:

8-8 Nov. 2005