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A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

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4 Author(s)
Bashirullah, R. ; Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA ; Wentai Liu ; Cavin, R., III ; Edwards, D.

This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 μm CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 2 )

Date of Publication:

Feb. 2006

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