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A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation

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2 Author(s)
E. A. Crain ; MTL High Speed Circuits & Syst. Group, Massachusetts Inst. of Technol., Cambridge, MA, USA ; M. H. Perrott

A fast offset compensation method for high-gain amplifiers is presented that leverages a novel peak detector design and a dynamic, multi-tap feedback system to achieve roughly three orders of magnitude improvement in settling time over traditional compensation methods. Design tradeoffs between gain, bandwidth, power dissipation, and noise performance of the limit amplifier are discussed. Measured results of a custom 3.125 Gb/s limit amplifier in 0.18 μm CMOS employing the proposed compensation technique demonstrate a sub-1-ms settling time while still achieving less than 4 ps rms output jitter with a 2.5 mV peak-to-peak input at 2.5 Gb/s.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 2 )