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A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration

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2 Author(s)
A. Varzaghani ; Univ. of California, Los Angeles, CA, USA ; C. -K. K. Yang

The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mVp-p at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with ±0.35 LSB of DNL and ±0.15 LSB of INL. The 180 × 1500 μm2 chip is fabricated in a 0.18-μm standard CMOS technology and consumes 70 mW of power at 600 MS/s.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 2 )