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Double-residue modular range reduction for floating-point hardware implementations

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3 Author(s)
Villalba, J. ; Dept. of Comput. Archit., Malaga Univ., Spain ; Lang, T. ; Gonzalez, M.A.

In this paper, we present a novel algorithm and the corresponding architecture for performing range reduction, which is a preprocessing task required for the evaluation of some elementary functions such as trigonometric and exponential-based functions. The proposed algorithm introduces a modification to the modular range reduction algorithm which increases the speed of computation and allows us to design an architecture for the floating-point case. The implementation presented admits as an input argument any representable number of the standard single precision IEEE 754 floating-point representation and provides the maximum accuracy to the final result. This supposes a hardware solution to the problem of having an input argument close to a multiple of the constant. A final comparison with other implementations is presented.

Published in:

Computers, IEEE Transactions on  (Volume:55 ,  Issue: 3 )

Date of Publication:

March 2006

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