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High-performance single clock cycle CMOS comparator

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2 Author(s)
H. -M. Lam ; Dept. of Electron. & Electr. Eng., Hong Kong Univ. of Sci. & Technol., China ; C. -Y. Tsui

A novel comparison algorithm is introduced, which uses a parallel MSB checking method instead of the traditional priority-encoding based comparison algorithm. Fast dynamic NOR gates are used instead of high-fanin NAND gates and this results in significant improvement in performance over the traditional design. The design was realised in AMS 0.35 μm technology. It is shown that the proposed design is 22% faster than the existing fastest single-cycle comparator based on priority encoder.

Published in:

Electronics Letters  (Volume:42 ,  Issue: 2 )