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As the need for power reduction techniques based on on-chip dynamic voltage scaling is on the rise, a design flow that can take full advantage of the performance/power tradeoffs is required. In this paper, we present a scalable polynomial model (SPM) based approach to precisely estimate the power and performance achievable through voltage scaling techniques. The main challenge here is generating accurate scalable polynomial models for timing and power and coming up with the right usage methodology. Novel techniques have been employed to generate piecewise polynomials for any given set of data without loss of accuracy. A new approach for incrementing the polynomial orders for reduction in run time is presented along with results. SPM libraries were generated for an entire library and validated at the cell level and design level. A complete usage model for designs using dynamic voltage scaling is also presented.