Skip to Main Content
In this paper, a low-power ROM-less direct digital frequency synthesizer (DDFS) is presented. A preset value pipelined accumulator (PVPA) is proposed achieving update rates in excess of 500MHz by careful choice of the 12-7-7-6 4-stage pipelined architecture. Power dissipation is reduced by moving redundant registers and no phase latency is introduced when switching frequency. The phase to sine amplitude converter is entirely made up of combinational logic without ROM, and modified Sunderland approximation and power-gating technique are used to reduce its area and power, respectively. Moreover, a 2MSB truncated phase is introduced to one-quadrant phase to sine amplitude converter to improve the spurious free dynamic rang (SFDR) by 10dB. The design was implemented using a 0.18 μm CMOS technology. It occupies a core area of 0.04mm2 and dissipates 17.2mW at 1.8 V supply voltage and 500 MHz clock.