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This paper proposes a chaotic system as a truly random number generator that can be fully integrated in a crypto processor. The chaotic system is composed of four pipelined switched-current circuits based on a simple piecewise-linear one-dimensional map. The optimum parameters of the map are analyzed to avoid certain circuits being locked at the parasitic stable points. As a necessary building block in a crypto processor, a hardware SHA-1 module is utilized to post-process the original bits generated by the chaotic system. The whole design is realized in TSMC 0.25 μm CMOS mixed signal process, and the randomness has been proved by simulations. The analog part of the design is clocked at 10 MHz and the digital part at 143 MHz. The ultimate truly random output bit rate is 200 Mbit/s.
Date of Conference: 3-7 Jan. 2006