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An efficient scan tree design for compact test pattern set

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3 Author(s)
Banerjee, S. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; Chowdhury, D.R. ; Bhattacharya, B.B.

Various designs of scan paths based on tree-like structures have recently been suggested for reducing test application time or test data volume in today's high density VLSI circuits. Most of these techniques strongly rely on the existence of a large number of compatible sets of flip-flops under the given test set, and therefore, are unsuitable for highly compact test sets generated by efficient ATPG tools. In this paper, to circumvent this problem, a new two-pass hybrid method is proposed to design an efficient scan tree architecture. Given a compact test set, compatibility relationships among the flip-flops are first explored, and a graph-based heuristic algorithm is employed to construct a scan tree with minimal incompatibility. Next, the same combinational ATPG tool is rerun to generate a new test set satisfying the logical constraints on the secondary inputs imposed by the structure of the scan tree. To cover the remaining hard-to-detect faults, if any, a few test vectors are chosen from the original test set for application in the serial mode. Experimental results on various benchmark circuits demonstrate that the proposed algorithm outperforms the earlier methods in reducing the total test application time significantly without any degradation of fault coverage.

Published in:

VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on

Date of Conference:

3-7 Jan. 2006